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# First-Term Examination

Fifth Semester [B.Tech] - September 2005

 Paper Code : ETCS – 305 Subject : Computer Architecture
 Time : 11/2 Hours Maximum Marks : 30
 Note : Attempt any 3 questions in all. Q1 is compulsory. Each question carries 10 marks.

 Q1 ( a ) How many bits wide memory addresses have to be if the computer had 16 MB of memory? (Use the smallest value possible) 1 ( b ) Derive the correct floating point representation of the decimal numbers +3.5 and -2.1 using the 32 bit IEEE 754 floating point standard. 2 ( c ) Consider the following floating points: Mantissa of X = 110011,  Exponent of X = 1100111 Mantissa of Y = 000001,  Exponent of Y = 1101111 Perform operations X + Y. 1.5 ( d ) Differentiate between Selective repeat Set and Selective Compliment. 2 ( e ) The following transfer statements specify a memory. Explain the memory operation in each case i) R2 <- M[AR]    ii) M[AR] <- R3 1.5 ( f ) Differentiate between Classical method and One Hot method of Control Design. 1.5

Q2

( a )

Design an arithmetic circuit with one selection input S and two n-bit data inputs A and B. The circuit generates the following four arithmetic operations:

 S Cin=0 Cin=1 0 D = A + 1 D = A + B 1 D = A + B + 1 D = A - 1

1 + 4*1

( b )

A digital computer has a common bus system for 12 registers of 9 bits each. The bus is constructed with multiplexers.

1. How many selection inputs are there in each multiplexer? 

2. What size of multiplexers are needed? 

3. How many multiplexers are there in the bus? 

4. Draw a diagram of the bus system using three-state buffers and a decoder instead of multiplexers? 

 Q3 ( a ) The system uses a control memory of 1024 words of 32 bits each. The microinstruction has three fields for micro-operations. select a status bit and Brach address field. The micro-operation field has 16 bits. How many bits are there in the branch address field and select field? If there are 16 status bits in the system, how many bits of the branch logic are used to select a status bit? How many bits are left to select the input to the multiplexers? 2+2+1 ( b ) The contents of the PC in the basic computer is 3AF (all numbers in HEX). The contents of AC are 7EC3. The contents of memory at address 3AF are 09AC. The contents of memory at address 9AC is 8B9F. Assume op-code 001 stands for ADD operation. What is the instruction that will be fetched and executed next? Show the binary operation that will be performed? Give the contents of registers PC, AR, DR, AC and IR in hexadecimal at the end of the instruction cycle. 0.5 + 0.5 + 4

 Q4 ( a ) Write a program to evaluate the arithmetic statement: Using a general register computer with three address instructions. Using an accumulator type computer with two address instructions. Using an accumulator type computer with one address instructions. Using a stack organized computer with zero address instructions. 5 ( b ) A two word instruction is stored in memory at an address designated by the symbol W. The address field of the instruction (stored at W+1) is designated by the symbol Y. The operand used during the execution of the instruction is stored at an address symbolized by Z. An index register contains the value X. State how Z is calculated from the other addresses if the addressing mode of the instruction is: (Give explanation also) Direct Indirect Relative Indexed Immediate 1*5