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First-Term Examination

Fifth Semester [B.Tech] - September 2005

Paper Code : ETEC – 301 Subject : Digital Circuit and Systems I

Time : 11/2 Hours

Maximum Marks : 30

Note : Attempt any 3 questions in all. Q1 is compulsory. Each question carries 10 marks.

Q1

( a )

How are hazards avoided using SR latches.

2

( b )

Distinguish between Mealy model and Moore model. 1
( c ) A sequential circuit has two JK flip flops A and B, on input y, and one output y. The J and K inputs are defined as:

Ja = B, Kz = B', Jb = Kb = (xA' + x'A)'
y = ((x'A + xA')B' + (xA' + x'A)'B)

Derive the state table.

3
( d ) What are cycles in asynchronous circuits. Give examples. 2
( e ) Assign output values to the dont care conditions in the following flow tale:
  00 01 11 10
A D,- A,0 A,0 B,-
B B,1 B,1 C,- B,1
C B,- C,1 C,1 D,-
D D,0 D,0 A,- D,0
2

Q2

( a )

A sequential network has one input (X) and one output (Z). The network examines groups of four consecutive inputs and produces an output Z=1 if the input sequence 0101 or 1001 occurs. The network resets after every four inputs. Determine the mealy state graph and state table.

6

( b )

Draw an ASM chart that specifies a conditional operator to increment register R during state T1 and transfer to state T2 if control inputs z and y are equal to 1 and 0 respectively.

4

Q3

( a )

Determine the state table corresponding to the following state diagram:

state diagram

3

( b )

Design an asynchronous sequential circuit with two inputs x1 and x2 and one output z. initially both inputs and outputs are equal to 0. When x1 or x2 becomes 1, z becomes 1. When the second input also becomes 1, the output becomes 0. The output stays at 0 until the circuit foes back to the initial state.
  1. Obtain the primitive flow table and show that it can be reduced to the following flow table:
     
      00 01 11 10
    A A,0 A,1 B,- A,1
    B A,- B,0 B,0 B,0
  2. Design the circuit using SR latches.
 

Q4

( a )

USE IMPLICATION TABLE TO REDUCE THE FOLLOWING TABLE TO A MINIMUM NUMBER OF STATES:
 
PRESENT STATE NEXT STATE OUTPUT
X=0 X=1 Z
A F D 0
B D A 1
C H B 0
D B C 1
E G B 0
F A H 0
G E C 0
H C F 0

3

( b )

The state diagram of a control unit is as shown below. It has four states and two inputs x and y.

state diagram

  1. Draw the equivalent ASM chart
  2. Design the control unit using D flip flops and decoders.
7

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