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Fifth Semester [B.Tech] - November 2005
Paper Code : ETEC – 303 Subject : Microprocessor System I |
Time : 11/2 Hours |
Maximum Marks : 30 |
Note : Attempt any 3 questions in all. Make suitable assumptions where nessecary. |
Q1 |
( a ) |
The memory space of an 8085A based system consists of one 8Kx8 bit EPROM starting from memory locations 0000H to 1FFFH and 8 RAM chips each of 1Kx4 bits from the location 2000H. Draw the decoding circuit and draw the connection diagram. |
3 |
( b ) |
Discuss the various mapping techniques used to establish the relationship between the main memory and cache memory blocks. | 4 | |
( c ) |
Consider the memory system with main memory size = 8K blocks; cache
memory size = 512 blocks; block size = 8 words. Determine the size
of the tag field of the main memory address under the following
conditions:
|
3 |
Q2 |
( a ) |
Discuss the modes in which the Programmable Peripheral Interface device 8255A can be operated. |
3 |
( b ) |
Determine the 8255 control word to be used when programming the port A as mode1 input port and port B as mode1 output port. INTEA and INTEB should both be enabled and the two unused port C lines should be defined as outputs. Address of the control port is 83H. Draw the Connection diagram and write the initialization routine required. |
3 | |
(c) | Specify the handshake signals for port B of the 8155 if port B is connected as an input port in interrupt mode. Explain the functioning of each handshake signal. | 4 |
Q3 |
( a ) |
Draw the connection diagram to show how the DMA controller 8237 can be interfaced with the 8-bit microprocessor 8085A and list the steps required to accomplish data transfer with the peripheral. |
5 |
( b ) |
Draw the block diagram of the Programmable Keyboard/Display Interface 8278 and explain its operation. Discuss the format of the keyboard/display mode set command. | 5 |
Q4 |
Write short notes on : |
10 |
|
( a ) |
Cache Controller |
3 |
|
( b ) |
DRAM Controller |
4 |
|
( c ) |
Programmable Interval Timer, 8254 |
|