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First-Term Examination

Sixth Semester [B.Tech] - February 2006

Paper Code : ETEC – 310 Subject : VLSI Design

Time : 11/2 Hours

Maximum Marks : 30

Note : Attempt any 3 questions in all. Q1 is compulsory. Each question carries 10 marks.

Q1

( a )

With a neat flow diagram discuss the VLSI design methodology.

2

( b )

Describe in brief about regularity, modularity and locality. 2
( c ) Advantages and disadvantages of standard-cells based design. 2
( d ) Noise margin in MOSFET inverter. 2
( e ) Draw a neat diagram (isometric/oblique view) of  an N-channel enhancement type MOSFET. 2

Q2

( a )

Discuss in brief about:

  1. Photolithography
  2. Metallization and Polysilicon
  3. Device isolation techniques
  4. CMOS n-well process.

10

Q3

( a )

Write in brief about:
  1. Law of mass action
  2. Equilibrium Fermi level
  3. Surface inversion
  4. Threshold voltage
  5. Channel length modulation

5

( b )

Derive the following relationship of an N-channel MOSFET:

(Where the notations have their usual meaning.)

 

Q4

( a )

Discuss in detail the CMOS inverter with a resistive load and critical factors that affect the layout design.

10

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